The following code models a four-bit parallel in shift left register with load and shift enable signal. Module Parallelinserialoutloadenablebehavior(input Clk, input ShiftIn, input 3:0 ParallelIn, input load, input ShiftEn, output ShiftOut, output. Serial or parallel output. The shift register output mode may be: serial: only the contents of the last flip-flop is accessed by the rest of the circuit parallel: the contents of one or several of flip-flops other than the last one, is accessed shift modes: left, right, etc. There are different ways to describe shift registers. The following code models a four-bit parallel in shift left register with load and shift enable signal. Module Parallelinserialoutloadenablebehavior(input Clk, input ShiftIn, input 3:0 ParallelIn, input load, input ShiftEn, output ShiftOut, output. Design of Serial In - Parallel Out Shift Register using D-Flip Flop (VHDL Code). 11:19 naresh.dobal 3 comments Email This BlogThis!
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Shift Register using verilog |
4 Bit Shift Register Verilog
I wrote a parallel in serial out shift register, which I present here. Module shiftreg32b (clk, reset, shift, carrega, in, regout); input clk; input reset, shift; input to an output in a combinational module in Verilog Verilog Illegal Reference to net 'OUT' What does this Verilog module do? It contains many explicit features which include parallel inputs, parallel outputs, synchronous reset, bidirectional serial input and bidirectional serial output. The below presented verilog code for 4-bit universal shift register acts as a uni-directional shift register for serial-in and serial-out mode,. Verilog Code for Parallel in Parallel Out Shift Register - Free download as Word Doc (.doc /.docx), PDF File (.pdf), Text File (.txt) or read online for free.
We will now consider a shift register. Our shift register has an s_in input entering on its left hand side. At each clock cycle, the content of the register shifts to the right and s_in enters into the leftmost bit or the MSB bit. The whole design also has and output that we are c calling s_out. At each clock cyccle the right most bit of the register comes out.
The picture shows the scheme of the shift register.
Here is the verilog implemmentation of shift register.
Explanation |
Initially the reg value of undefined and hence we have placed 4'bxxxx in its value.
Because of the assign statement
the initial value of s_reg[0] is also 0.
When the reset pulse is applied the r_reg becomes 0000 at the next rising edge of clock. Note that the period of the negative level of the reset sould last at least to the next rising edge of the clock
At this stage, the value of s_out also becomes 0 ( right after the rising edge of the clock).
Now the s_in value is supplied sometimes before the next rising edge of the clock. Now because of the assign statement
the wire r_next is driven by the value of s_in and [3:1] bits of r_reg.
And so, after the application of the s_in, at the next rising edge of the clock, the statement
in the always loop takes effect. which essentially results in updating the r_reg value with its value shifted to right and s_in coming in at its MSB.
The testbech for the Serial shift register
Serial Input Serial Output Shift Register
Exercizes1. In test bench the shift register is instantiated with N=2. Verify that it behaves as expected. Repead the testbench and verification for N=4
Shift Register In Verilog
2. Write the above code for left shift in place of right shift. The data now comes out of the MSB. The data enters from LSB.
Parallel Load Shift Left Register verilog code
This page covers Parallel Load Shift Left Register verilog code and test bench code of Parallel Load Shift Left Register.
Parallel Load Shift Left Register verilog code
Shift Left Register Verilog
Following is the verilog code of Parallel Load Shift Left Register.
module plsl(pl, sl, slin, Din, clk, reset, Q);
input pl, sl, slin, clk, reset;
input [7:0] Din;
output [7:0] Q;
reg [7:0] Q;
always @ (posedge clk) begin
if (~reset) begin
if (sl) begin
Q <= 'TICK {Q[6:0],slin};
end
else if (pl) begin
Q <= 'TICK Din;
end
end
end
always @ (posedge reset) begin
Q <= 8'b00000000;
end
endmodule
input pl, sl, slin, clk, reset;
input [7:0] Din;
output [7:0] Q;
reg [7:0] Q;
always @ (posedge clk) begin
if (~reset) begin
if (sl) begin
Q <= 'TICK {Q[6:0],slin};
end
else if (pl) begin
Q <= 'TICK Din;
end
end
end
always @ (posedge reset) begin
Q <= 8'b00000000;
end
endmodule
Test code for Parallel Load Shift Left Register
Following is the test bench code of Parallel Load Shift Left Register.
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module main;
reg clk, reset, slin, sl, pl;
reg [7:0] Din;
wire [7:0] q;
plsl plsl1(pl, sl, slin, Din, clk, reset, Q);
initial begin
forever begin
clk <= 0;
#5
clk <= 1;
#5
clk <= 0;
end
end
initial begin
reset = 1;
#12
reset = 0;
#90
reset = 1;
#12
reset = 0;
end
initial begin
sl = 1;
pl = 0;
Din = 8'h42;
#50
sl = 0;
#12
pl = 1;
#5
Din = 8'h21;
#20
pl = 0;
sl = 1;
end
initial begin
forever begin
slin = 0;
#7
slin = 1;
#8
slin = 0;
end
end
endmodule
reg clk, reset, slin, sl, pl;
reg [7:0] Din;
wire [7:0] q;
plsl plsl1(pl, sl, slin, Din, clk, reset, Q);
initial begin
forever begin
clk <= 0;
#5
clk <= 1;
#5
clk <= 0;
end
end
initial begin
reset = 1;
#12
reset = 0;
#90
reset = 1;
#12
reset = 0;
end
initial begin
sl = 1;
pl = 0;
Din = 8'h42;
#50
sl = 0;
#12
pl = 1;
#5
Din = 8'h21;
#20
pl = 0;
sl = 1;
end
initial begin
forever begin
slin = 0;
#7
slin = 1;
#8
slin = 0;
end
end
endmodule
Verilog source codes
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Asynchronous FIFO design with verilog code
D FF without reset
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